Thursday, 16 August 2012

Experience designing the simplest CPU

With a textbook, good Altera Quartus II tutorial, from the vendor,
Terasic for the DE2-115, I thought I can easily design and test the
mano risc cpu.

In just a few hours, finished, but on compiling, no output at all.
Spent the next few hours deleting parts one by one, and yet, until
only the PLL oscillator left, still no output. The PLL was the same as
in the tutorial and yet no problem previously. Whatever the probem, it
was not due to the design. Must be some sort of licensing problems. I
use the free web edition of the Altera Quartus using the Megawizard
functions, in Verilog. The vendor tutorial uses Verilog.

The mano risc design looked simple until we actually implement it.
risc design requires 3-port RAM. Altera free edition only provides 2-
ported RAM. Luckily searching the internet provides inspiration for a
3-port design using a 2-ported RAM. No wonder RISC style of GP
registers was not popular in the early days. This 3-port design is
also the secret of RISC performance.

The book is almost complete, except the PC portion. Initially I wanted
to simplify it by using only branch on zero only, but adding the
negative condition is simple. I don't think it is wise to implement a
relative jump so I changed it to just offset jump, like PIC.

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